? semiconductor components industries, llc, 2004 august, 2004 ? rev. xxx 1 publication order number: MTW20N50E/d MTW20N50E preferred device power mosfet 20 amps, 500 volts n?channel to?247 this high voltage mosfet uses an advanced termination scheme to provide enhanced voltage?blocking capability without degrading performance over time. in addition, this advanced power mosfet is designed to withstand high energy in the avalanche and commutation modes. the new energy efficient design also offers a drain?to?source diode with a fast recovery time. designed for high voltage, high speed switching applications in power supplies, converters and pwm motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. ? robust high voltage termination ? avalanche energy specified ? source?to?drain diode recovery time comparable to a discrete fast recovery diode ? diode is characterized for use in bridge circuits ? i dss and v ds(on) specified at elevated temperature ? isolated mounting hole reduces mounting hardware maximum ratings (t c = 25 c unless otherwise noted) rating symbol value unit drain?source voltage v dss 500 vdc drain?gate voltage (r gs = 1.0 m w ) v dgr 500 vdc gate?source voltage ? continuous ? non?repetitive (t p 10 ms) v gs v gsm 20 40 vdc vpk drain current ? continuous drain current ? continuous @ 100 c drain current ? single pulse (t p 10 m s) i d i d i dm 20 14.1 60 adc apk total power dissipation derate above 25 c p d 250 2.0 watts w/ c operating and storage temperature range t j , t stg ?55 to 150 c single pulse drain?to?source avalanche energy ? starting t j = 25 c (v dd = 100 vdc, v gs = 10 vdc, i l = 20 apk, l = 10 mh, r g = 25 w ) e as 2000 mj thermal resistance ? junction to case thermal resistance ? junction to ambient r q jc r q ja 0.50 40 c/w maximum lead temperature for soldering purposes, 1/8 from case for 10 seconds t l 260 c device package shipping ordering information MTW20N50E to?247 30 units/rail preferred devices are recommended choices for future use and best overall value. ll = location code y = year ww = work week MTW20N50E llyww http://onsemi.com marking diagram & pin assignment d g to?247ae case 340k style 1 n?channel s 20 amperes 500 volts r ds(on) = 240 m w 1 2 3 4 1 gate 3 source 4 drain 2 drain
MTW20N50E http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics drain?source breakdown voltage (v gs = 0 vdc, i d = 250 m adc) temperature coefficient (positive) v (br)dss 500 ? ? 583 ? ? vdc mv/ c zero gate voltage drain current (v ds = 500 vdc, v gs = 0 vdc) (v ds = 500 vdc, v gs = 0 vdc, t j = 125 c) i dss ? ? ? ? 10 100 m adc gate?body leakage current (v gs = 20 vdc, v ds = 0) i gss ? ? 100 nadc on characteristics (note 1.) gate threshold voltage (v ds = v gs , i d = 250 m adc) temperature coefficient (negative) v gs(th) 2.0 ? 3.0 7.0 4.0 ? vdc mv/ c static drain?source on?resistance (v gs = 10 vdc, i d = 10 adc) r ds(on) ? 0.20 0.24 ohm drain?source on?voltage (v gs = 10 vdc) (i d = 20 adc) (i d = 10 adc, t j = 125 c) v ds(on) ? ? 5.75 ? 6.0 6.0 vdc forward transconductance (v ds = 15 vdc, i d = 10 adc) g fs 11 16.2 ? mhos dynamic characteristics input capacitance (v 25 vd v 0vd c iss ? 3880 6950 pf output capacitance (v ds = 25 vdc, v gs = 0 vdc, f = 1.0 mhz ) c oss ? 452 920 reverse transfer capacitance f = 1 . 0 mhz) c rss ? 96 140 switching characteristics (note 2.) turn?on delay time t d(on) ? 29 55 ns rise time (v dd = 250 vdc, i d = 20 adc, v gs =10vdc t r ? 90 165 turn?off delay time v gs = 10 vdc, r g = 9.1 w ) t d(off) ? 97 190 fall time r g 9.1 w ) t f ? 84 170 gate charge (see figure 8) q t ? 100 132 nc (v ds = 400 vdc, i d = 20 adc, v gs = 10 vdc) q 1 ? 20 ? v gs = 10 vdc) q 2 ? 44 ? q 3 ? 36 ? source?drain diode characteristics forward on?voltage (note 1.) (i s = 20 adc, v gs = 0 vdc) (i s = 20 adc, v gs = 0 vdc, t j = 125 c) v sd ? ? 0.916 0.81 1.1 ? vdc reverse recovery time (s fi 14) t rr ? 431 ? ns (see figure 14) (i 20 adc v 0 vdc t a ? 272 ? (i s = 20 adc, v gs = 0 vdc, di s /dt = 100 a/ m s) t b ? 159 ? reverse recovery stored charge di s /dt = 100 a/ m s) q rr ? 6.67 ? m c internal package inductance internal drain inductance (measured from the drain lead 0.25 from package to center of die) l d ? 5.0 ? nh internal source inductance (measured from the source lead 0.25 from package to source bond pad) l s ? 13 ? nh 1. pulse test: pulse width 300 m s, duty cycle 2%. 2. switching characteristics are independent of operating junction temperature.
MTW20N50E http://onsemi.com 3 typical electrical characteristics r ds(on) , drain-to-source resistance (normalized) r ds(on) , drain-to-source resistance (ohms) r ds(on) , drain-to-source resistance (ohms) 048121620 0 16 24 32 40 v ds , drain-to-source voltage (volts) figure 1. on?region characteristics i d , drain current (amps) 2.0 2.8 3.6 4.4 5.2 6.0 0 16 24 32 40 i d , drain current (amps) v gs , gate-to-source voltage (volts) figure 2. transfer characteristics 0 8 16 24 32 40 0 0.1 0.3 0.4 0.6 0 8 16 24 32 40 0.24 0.26 0.28 0.30 0.34 i d , drain current (amps) figure 3. on?resistance versus drain current and temperature i d , drain current (amps) figure 4. on?resistance versus drain current and gate voltage -50 0 0.8 1.6 2.4 0 100 200 300 400 500 1 10 100 1000 10000 t j , junction temperature ( c) figure 5. on?resistance variation with temperature v ds , drain-to-source voltage (volts) figure 6. drain?to?source leakage current versus voltage i dss , leakage (na) -25 0 25 50 75 100 125 150 t j = 25 c v ds 10 v 100 c 25 c t j = - 55 c t j = 100 c 25 c -55 c t j = 25 c v gs = 0 v v gs = 10 v v gs = 10 v 8 v 7 v 6 v 5 v 2 6 10 14 18 8 8 2.4 3.2 4.0 4.8 5.6 6.8 6.4 0.2 0.5 4 12202836 0.32 4 12202836 0.4 1.2 2.0 50 150 250 350 450 v gs = 10 v 15 v 100 c 25 c t j = 125 c v gs = 10 v i d = 10 a 9 v
MTW20N50E http://onsemi.com 4 power mosfet switching switching behavior is most easily modeled and predicted by recognizing that the power mosfet is charge controlled. the lengths of various switching intervals ( d t) are determined by how fast the fet input capacitance can be charged by current from the generator. the published capacitance data is difficult to use for calculating rise and fall because drain?gate capacitance varies greatly with applied voltage. accordingly, gate charge data is used. in most cases, a satisfactory estimate of average input current (i g(av) ) can be made from a rudimentary analysis of the drive circuit so that t = q/i g(av) during the rise and fall time interval when switching a resistive load, v gs remains virtually constant at a level known as the plateau voltage, v sgp . therefore, rise and fall times may be approximated by the following: t r = q 2 x r g /(v gg ? v gsp ) t f = q 2 x r g /v gsp where v gg = the gate drive voltage, which varies from zero to v gg r g = the gate drive resistance and q 2 and v gsp are read from the gate charge curve. during the turn?on and turn?off delay times, gate current is not constant. the simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an rc network. the equations are: t d(on) = r g c iss in [v gg /(v gg ? v gsp )] t d(off) = r g c iss in (v gg /v gsp ) the capacitance (c iss ) is read from the capacitance curve at a voltage corresponding to the off?state condition when calculating t d(on) and is read at a voltage corresponding to the on?state when calculating t d(off) . at high switching speeds, parasitic circuit elements complicate the analysis. the inductance of the mosfet source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. the voltage is determined by ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. the mosfet output capacitance also complicates the mathematics. and finally, mosfets have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. the resistive switching time variation versus gate resistance (figure 9) shows how typical switching performance is affected by the parasitic circuit elements. if the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. the circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. power mosfets may be safely operated into an inductive load; however, snubbing reduces switching losses. 10 5 0 15 20 25 gate-to-source or drain-to-source voltage (volts) c, capacitance (pf) figure 7a. capacitance variation 9000 8000 7000 4000 3000 2000 1000 0 v gs v ds t j = 25 c figure 7b. high voltage capacitance variation v ds , drain-to-source voltage (volts) 10 100 1000 10000 1000 100 10 c, capacitance (pf) c iss c oss c rss v ds = 0 v v gs = 0 v t j = 25 c v gs = 0 v 6000 5000 510 c oss c iss c iss c rss c rss
MTW20N50E http://onsemi.com 5 drain?to?source diode characteristics 0.50 0.54 0.58 0.62 0.66 0.94 0 4 8 12 20 v sd , source-to-drain voltage (volts) figure 10. diode forward voltage versus current i s , source current (amps) figure 9. resistive switching time variation versus gate resistance r g , gate resistance (ohms) 1 10 100 1000 100 10 t, time (ns) v dd = 250 v i d = 20 a v gs = 10 v t j = 25 c t r t f t d(off) t d(on) v gs = 0 v t j = 25 c figure 8. gate?to?source and drain?to?source voltage versus total charge 500 v gs , gate-to-source voltage (volts) 400 300 200 100 0 0 8 6 0 q g , total gate charge (nc) v ds , drain-to-source voltage (volts) 10 4 2 10 20 80 90 100 i d = 20 a t j = 25 c v ds 30 40 50 60 70 0.74 0.78 0.82 0.86 0.90 0.70 q3 q1 q2 qt v gs 16 safe operating area the forward biased safe operating area curves define the maximum simultaneous drain?to?source voltage and drain current that a transistor can handle safely when it is forward biased. curves are based upon maximum peak junction temperature and a case temperature (t c ) of 25 c. peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in an569, atransient thermal resistance?general data and its use.o switching between the off?state and the on?state may traverse any load line provided neither rated peak current (i dm ) nor rated voltage (v dss ) is exceeded and the transition time (t r ,t f ) do not exceed 10 m s. in addition the total power averaged over a complete switching cycle must not exceed (t j(max) ? t c )/(r q jc ). a power mosfet designated e?fet can be safely used in switching circuits with unclamped inductive loads. for reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. the energy rating decreases non?linearly with an increase of peak current in avalanche and peak junction temperature. although many e?fets can withstand the stress of drain?to?source avalanche at currents up to rated pulsed current (i dm ), the energy rating is specified at rated continuous current (i d ), in accordance with industry custom. the energy rating must be derated for temperature as shown in the accompanying graph (figure 12). maximum energy at currents below rated continuous i d can safely be assumed to equal the values indicated.
MTW20N50E http://onsemi.com 6 safe operating area t j , starting junction temperature ( c) e as , single pulse drain-to-source figure 12. maximum avalanche energy versus starting junction temperature 0.1 1.0 1000 v ds , drain-to-source voltage (volts) figure 11. maximum rated forward biased safe operating area 0.1 1.0 10 100 avalanche energy (mj) i d , drain current (amps) r ds(on) limit thermal limit package limit 0.01 0 25 50 75 100 125 10 2000 600 400 200 i d = 20 a 800 100 150 t, time (s) figure 13. thermal response r(t), normalized effective transient thermal resistance r q jc (t) = r(t) r q jc d curves apply for power pulse train shown read time at t 1 t j(pk) - t c = p (pk) r q jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 figure 14. diode reverse recovery waveform di/dt t rr t a t p i s 0.25 i s time i s t b 100 m s 10 m s 1 ms 10 ms dc d = 0.5 0.2 0.1 0.05 0.02 0.01 single pulse 1000 1600 1400 1200 1800 1.0e-05 1.0e-01 0.01 0.1 1.0 0.001 1.0e-03 1.0e-02 1.0e+01 1.0e+00 1.0e-04 v gs = 20 v single pulse t c = 25 c
MTW20N50E http://onsemi.com 7 package dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. style 1: pin 1. gate 2. drain 3. source 4. drain r p a k v f d g u l e 0.25 (0.010) m tb m 0.25 (0.010) m yq s j h c 4 123 ?t? ?b? ?y? ?q? dim min max min max inches millimeters a 19.7 20.3 0.776 0.799 b 15.3 15.9 0.602 0.626 c 4.7 5.3 0.185 0.209 d 1.0 1.4 0.039 0.055 e 1.27 ref 0.050 ref f 2.0 2.4 0.079 0.094 g 5.5 bsc 0.216 bsc h 2.2 2.6 0.087 0.102 j 0.4 0.8 0.016 0.031 k 14.2 14.8 0.559 0.583 l 5.5 nom 0.217 nom p 3.7 4.3 0.146 0.169 q 3.55 3.65 0.140 0.144 r 5.0 nom 0.197 nom u 5.5 bsc 0.217 bsc v 3.0 3.4 0.118 0.134 to?247 case 340k?01 issue c
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